Design of LCD Driver Circuit of Smart Phone Based on PXA27x
The design of the LCD screen is directly related to the overall performance of the smartphone. However, there are many types of LCD screens, and engineers need to design for the timing matching of various displays, power requirements, and the different characteristics of the controller. This article introduces the characteristics of the integrated LCD controller inside the PXA27x, the drive implementation method and the related power supply design, and puts forward EMC design recommendations.
The global smartphone market is in a period of rapid growth. Market research company Gartner predicts that with the decline in demand for handheld computers, global smartphone sales will grow to 14 million units in 2004, with a growth rate of 140%. It is expected to be substantial by 2007 Grew to 45 million. Facing the growing smartphone market, various chip manufacturers have successively launched chip solutions with their own characteristics: such as i of Freescale. The MX21 processor embeds multimedia acceleration technology and supports MPEG4 and H. 263; IntelPXA27xBulverde processor embedded MMX technology and SpeedStep power saving technology, support MPEG4, MP3 decoding and 4 million pixel camera. Multimedia applications have also become a highlight of next-generation mobile phones. Watching movies, watching TV, and playing games on mobile phones is the development trend of next-generation mobile phones.
IntelPXA27x is a processor with good multimedia application effect. Using this processor can even enable end users to get 3D gaming experience on mobile communication devices. The design effect of the LCD screen, which can be called the eyes of a smartphone, is undoubtedly one of the most important factors for consumers to choose. The following is a detailed introduction to the design and implementation of LCD in smart phones based on PXA27x processors.
LCD screen design
The LCD hardware design circuit based on the PXA27x processor is shown in the figure, which is mainly composed of three parts: the LCD controller, the timing ICLZ9FC22 and the liquid crystal display LCD.
The PXA27X processor integrates an LCD controller and supports a variety of LCD screens, such as dual-scan passive array display (DSTN-LCD) and thin film transistor active array display (TFT-LCD). The main features are: support for single or dual scan display mode, embedded frame buffer, up to 8-bit passive dual scan display mode, support for up to 18-bit pixel single-screen display panel without embedded frame cache, support for up to 24-bit pixels Single-screen display panel with embedded frame buffer.
The controller has three display types:
Passive color mode, supporting 16777216 (24-bit) colors;
Active color mode, support 16777216 (24-bit) colors;
Passive black and white mode, support 256 (8-bit) grayscale.
The LCD controller supports displays up to 800 × 600 pixels. However, in the frame memory, the size of the display screen that can be driven is limited by the bus width of the memory and the size of the pixel encoded data.
Frame and palette data can be stored in the embedded SRAM or external memory. The LCD DMA controller has a total of 7 DMA channels. The frame and palette data can be loaded through these 5 DMA channels 0-4 Enter 16 × 6? Bits in the input FIFO (first in first out). Through the internal system bus, the DMA channel 5 can be used to store the pixel encoded data in the external frame memory or embedded SRAM to the relevant 16 × 6? Bit input FIFO. The LCD controller uses it as a pointer to index a small palette of 4 × 24 bits wide, and gets 24-bit pixel color. DMA channel 6 is used to transfer command data, and transfer and store the command data stored in the external memory or the frame header of the SRAM inside the LCD panel in the 4 × 52-bit command FIFO.
According to the different display types to be connected, the LCD controller can be programmed to the corresponding working mode: when connected to a black and white screen, it can be configured into 4, 8-bit mode; connected passive color screen has 8-bit and 16-bit working modes; When connected to an active color screen, the controller can be configured to work in 12, 16, and 18 bits.
Our LCD screen design program selected the active color mode, using Sharp's 3.5-inch TFT active color liquid crystal display LQ035Q7DB02, using a 16-bit working mode, RGB565. Due to the wide variety of LCD screens of handheld devices, the inconsistency of the standards of various manufacturers makes the LCD controller of PXA27X and Sharp 3.5-inch screen unable to match the data format and display timing. Therefore, it is necessary to select a timing control IC or use CPLD to map data interfaces of different data formats. Here, our timing control IC uses LZ9FC22.
The PXA27XLCD controller consists of the following pins:
LDD [15? 0]: 16-bit data line, the data lines of R, G, and B chrominance signals are 5, 5, and 6 bits, respectively;
L_PCLK: pixel clock (Pixelclock), used to send the data of each point into the shift register, the maximum clock can reach 52MHz;
L_LCLK: line clock, used to indicate that a line of data has been transferred from the shift register to the display driver chip, and increments the line pointer. In 16-bit TFT mode, it is a horizontal synchronization signal;
L_FCLK: frame clock, used to indicate the start of a frame of image, and put the line pointer on the first line of the display screen. In the 16-bit TFT mode, it is a vertical synchronization signal;
L_BIAS: In the 16-bit TFT mode, the output enable signal is used to indicate that the data signal is latched to the pin in synchronization with the clock signal.
In order to display a frame of image, the PXA27XLCD controller first stores the image data to be displayed in the frame buffer, and then makes the DMA address register of the LCD controller point to the start address of the frame buffer, and reads the data in the frame buffer to Enter the FIFO queue. Because the 16-bit mode is used in this design, there is no need to decode the data in the frame buffer, so the LCD controller directly sends the data to the output FIFO without processing, and the output FIFO sends the data to the LZ9FC22 through the pin to drive the liquid crystal display .
LCD power supply design
This LCD design involves several power supplies, including VSHD (+ 3.3V), VSHA (+5), VDD (+ 15V) and VEE (-10V), and + 21.6V for backlight. Each voltage has a tolerance range. The voltage ranges are as follows:
+ 3.3V (3.0 ~ 3.6);
+ 5V (4.5 ~ 5.5);
+ 15V (14.5 ~ 15.5);
-10V (-10.5 ~ -9.5);
+ 21.6V (~ 24).
Except for the + 21.6V voltage used for backlighting, the rest of the power-on sequence is either switched simultaneously or in the order of turning on VSHD → VSHA → VEE → VDD and turning off VDD → VEE → VSHA → VSHD. The design of this project adopts the simultaneous mode. The LT1944-1 of Linear Technology Co., Ltd. can output three voltages of VSHA (+5), VDD (+ 15V) and VEE (-10V) at the same time. Shut down.
Electromagnetic compatibility design
In the design, in order to maintain the integrity of the LCD signal data and ensure the quality of the LCD screen output image, it is necessary to add some protection devices appropriately, and the PCB layout is also a factor. When wiring, the LCD data lines (that is, RGB lines) should be as short as possible, and the spacing between the lines should be large enough, such as maintaining at least twice the line width distance. Adding ESD / EMI protection devices to the LCD data line is relatively simple, and such devices are easy to find.
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