Abstract: Dallas Semiconductor's all-silicon delay lines provide a low-cost alternaTIve to the tradiTIonal delay line constructed of discrete components. This note briefly describes the differences in technology between the two types of delay lines and covers some of the issues required when designing an all-silicon delay line in as a replacement for a modular delay line.
As the availability of hybrid delay lines conTInues to decline, there is an increasing need for an alternaTIve approach. When system redesigns / upgrades occur, there is an opportunity to design in silicon replacements and alleviate these problems.
Maxim does not offer direct replacements for any passive delay lines. However, in many cases functional replacements are available, subject to certain limitations. Passive delays are, by nature, analog devices with respect to input and output characteristics, whereas the silicon upgrades are purely digital. Some passive delays are used in purely analog applications, in which case no replacement option exists. In other applications, passive delays are used in digital fashion but with reduced voltage levels (eg, ECL). Replacement in this case may be possible if a system redesign using regular TTL or CMOS levels is planned.
The critical effect of output loading of passive devices on in-system timing must be considered when planning a silicon solution replacement.
Finally, some passive devices are used to generate very small delays in the nanosecond range. Our current delay line implementation does not allow generation of less than approximately 3ns delay.
As the availability of hybrid delay lines conTInues to decline, there is an increasing need for an alternaTIve approach. When system redesigns / upgrades occur, there is an opportunity to design in silicon replacements and alleviate these problems.
Maxim does not offer direct replacements for any passive delay lines. However, in many cases functional replacements are available, subject to certain limitations. Passive delays are, by nature, analog devices with respect to input and output characteristics, whereas the silicon upgrades are purely digital. Some passive delays are used in purely analog applications, in which case no replacement option exists. In other applications, passive delays are used in digital fashion but with reduced voltage levels (eg, ECL). Replacement in this case may be possible if a system redesign using regular TTL or CMOS levels is planned.
The critical effect of output loading of passive devices on in-system timing must be considered when planning a silicon solution replacement.
Finally, some passive devices are used to generate very small delays in the nanosecond range. Our current delay line implementation does not allow generation of less than approximately 3ns delay.
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