Principle and application of KCPSM6 8-bit embedded processor

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The PiCOBlaze 8-bit embedded processor is an embedded processor soft core designed by Xilinx for Virtex, Spartan series FPGAs and CoolRunner - Series II CPLDs. For different devices, Xilinx has released three versions of PICoBlaze, including KCPSM3 (target devices are Spartan 3, Virtex II, Virtex II PRO, Virtex 4, and Virtex 5) CPLD version (target device is CoolRunner - II) and The latest KCPSM6 (target devices are Spartan 6, Virtex 6 and 7 series FPGAs). The KCPSM6 is specially optimized for Spartan 6, Virtex 6 and 7 series FPGAs, adding new features and differences in development and debugging methods from KCPSM3. This paper analyzes and compares its similarities and differences, summarizes the considerations of KCPSM6 in development and debugging, and carries out an example verification on Avnet Spartan 6 MicroBoard.

1 KCPSM6 PicoBlaze architecture
KCPSM6 PicoBlaze (hereinafter referred to as KCPSM6) 8-bit embedded processor is an embedded processor soft core designed by Xilinx for Spartan 6, Virtex 6 and 7 series FPGAs. It has the advantages of high efficiency and low resource consumption, which can be easily embedded. In the hardware system design, realize seamless connection with other functional modules. It occupies only 26 slices and 1 BRAM, accounting for 4.3% of the resources of the XC6SLX4 device and less than 0.11% of the resources of the XC6SLX150T device. The KCPSM6 embedded processor has an instruction execution speed of up to 52-120 MIPS, depending on the family of FPGAs selected and the device speed grade.
The KCPSM6 microprocessor consists mainly of the following units:
â—† Two sets of 16 8-bit general-purpose registers;
â—† Up to 4 KB of program storage unit;
â—† 8-bit arithmetic logic unit with CARRY and ZERO flags;
â—† 64, 128 or 256 bytes of internal temporary storage RAM;
â—† 256 inputs and 256 output ports for easy application expansion;
â—† interrupt control unit;
â—† Sleep mode, further reducing system power consumption.
The block diagram of the KCPSM6 embedded processor is shown in Figure 1.

The new features and functions of KCPSM6 are summarized as follows:
(1) New pin
Sleep pin. When the sleep pin level goes from low to high, KCPSM6 enters sleep mode after executing the last read command to reduce system power consumption. If the sleep pin is always low, the KCPSM6 is always in normal operation.
K_write_strobe is a constant output trigger signal. Used in conjunction with the OUTPUTK instruction, a constant value can be output to the output port with one instruction without register intervention.
Bram_enable is the program memory unit BRAM enable signal, which can further reduce system power consumption.
Address[11:10] is the high address line of the program memory unit and supports up to 4 KB of program memory.