In this paper, by directly configuring the internal PLL of the chip and the VENC timing generator, the pixel clock and synchronous control timing signals required for displaying high-definition digital video are generated. The output of VENC is finally realized by the DVI display interface provided by TFP410, and finally realizes 720P, 1080P and The high-definition digital video display under WUXGA resolution finally shows that the proposed scheme is easy to use, feasible and practical.
0 Preface
The DM6446 chip from TI is widely used in video processing. It is based on the ARM+DSP dual-core architecture and features both general-purpose processors (GPPs) and dedicated digital processors (DSPs). Its Video Processing Subsystem (VPSS) also includes an interface for video capture - the Video Processing Front End (VPFE) and the video display interface - Video Processing Backend (VPBE), which is also able to emerge in the video processing arena. An important part of. The DM6446 can support both digital and analog video output in standard timing PAL/NSTC mode. It also supports non-standard analog VGA display interface. However, the resolution of the video output is low, which is not suitable for applications requiring large resolution display.
In order for it to support high-definition display, it must be programmed to achieve the timing control signals required for high-definition display. The DM6446 supports parallel 24-bit RGB888 video data output, which is converted to an external chip and then sent to the display. The encoding chip used here is TFP410, which receives parallel image data and synchronous control signals. After being encoded and converted, it is transmitted to the display for display according to the DVI standard [5].
The first part of the paper introduces the overall structure of the HD digital video interface design; the second part introduces the configuration and use of the TFP410; the third part introduces the VENC parameter configuration method required to achieve high-definition digital display, combined with the OSD window configuration. The actual HD digital video display results are given.
On the target board, 720P (1 280&TImes; 720@60 Hz), 1 080P (1 920 & TImes; 1 080@60 Hz) and WUXGA (1 920 & TImes; 1 200@60 Hz) resolution digital video display can run stably It shows that the design scheme of the high-definition digital video display interface proposed here is correct and feasible, and has practical significance for the application based on DM6446 high-definition digital video display.
1 HD digital video display interface overall structure
The structure of the entire DVI HD digital video display interface is shown in Figure 1. It can be divided into two parts: the VPSS interface part of the DM6446 and the TFP410 interface of the DVI driver.
The VPFE collects video data from the outside and stores it in the specified location in DDR2. The on-screen display module (OSD) in VPBE also has a corresponding buffer in DDR2. The data transmission between these modules and DDR2 has a special read. Write logic control to ensure that the data transmission bandwidth meets the system requirements. For high-definition display support, it is mainly to correctly configure the timing control part of the video coding module (VENC) in VPBE, including VENC clock, OSD clock and pixel clock output to TFP410, as well as video line synchronization, field synchronization signal, etc. These will be described in detail later.
The TFP410 mainly plays the role of video data encoding. The image data and the synchronous control signal output by the VENC are encoded and transmitted to the display by differential serial (TMDS), which can ensure the anti-interference ability of the data during transmission. . At the same time, the TFP410 includes an I2C interface that allows the DSP to configure the operating mode of the DVI driver. After the system is powered up, the TFP410 can detect if the display is connected, so the DSP can determine whether to send video data by checking the corresponding status bits.
2 TFP410 working mode configuration
The TFP410 supports a maximum pixel clock of 165 MHz, which meets the needs of high-definition digital video display. There are two configuration methods in total:
Pin direct configuration method and I2C configuration method. Using the direct pin configuration method, the chip can work directly in the established mode after power-on, but the function is relatively simple and the working mode is not flexible enough. Using the I2C configuration method, the working mode of the chip can be adjusted as needed, including the clock edge of the data acquisition, the data bit width, and the data acquisition delay. By reading the relevant status registers in the TFP 410, the DSP-side application can also obtain information about the image transmission, including horizontal and vertical global resolution, and whether the display is connected.
TFP410 has a total of 256 I2C accessible registers, most of which are reserved. In actual use, there are a few registers that need to be operated. Here, you only need to configure the registers CTL_1_MODE, CTL_2_MODE, CTL_3_MODE, and others can be configured by default. Generally, there is no need to change them. Set CTL_1_MODE.
PD#=1 to restore the chip from power saving mode to normal mode; set CTL_1_MODE.HEN=1, CCTL_1_MODE.VEN=1 to enable line and field sync signal input, and set CCTL_1_MODE.TDIS=0 to enable chip TMDS circuit output. CTL_2_MODE is mainly used for the host to detect the display status, while CTL_3_MODE is mainly responsible for the delay control during the data acquisition process. The basic configuration process for TFP410 is shown in Figure 2.
In Figure 2, only the registers that must be configured are listed. The remaining registers can be modified without affecting the use. Configure CTL_1_MODE=0×37 to enable the device to operate in a 24-bit data width, single-ended pixel clock (VCLK) input, and sample input data on the rising edge of VCLK. After configuring the TFP410, the DM6446 can output the corresponding image data and synchronization control information according to the standard timing of high-definition digital video, and then display the content on the OSD to the LCD display through the DVI interface.
The Relay Module integrates and serializes the single small power library relay in the electrical control cabinet, reduces the intermediate wiring link and improves the product performance. The product conforms to the development trend of miniaturization and integration, and is the renewal product of the original single relay. The installation form adopts the general 35mm U-shaped guide rail for installation, which is convenient and fast.Our products are made of Idec, Omron, Tyco, Panasonic relay and deca terminal.
Transfers Module,Interface Products,CNC Interface Board,Control Relay Module
Suzhou WeBest Electronics Technology Co.Ltd , https://www.webestet.com