The sample obtained by first coating the silica gel and then coating the phosphor paste (sample 2) has the smallest difference between the front and the back, and the color temperature and chromaticity coordinates are close to each other; while the direct coating of the phosphor (sample 1) has the largest total luminous flux. However, the color temperature, color coordinate and luminous flux of the front and back sides are very different; the light source prepared by coating the silica gel doped with the diffusion powder and then coating the phosphor has the lowest total luminous flux, and the difference between the front and back luminous flux is larger than that of the sample 2.
The illuminating angles of the three samples were tested, and the illuminating angle distribution was similar, and the illuminating intensity was similar to the luminous flux ratio of the integrating sphere test. Therefore, the preparation process of the sample 2 is suitable for preparing a three-dimensional light-emitting lamp.
The market-oriented LED packaging technology is that the positive-loading chip is fixed in the concave cup by insulating glue or silver glue, and the positive and negative electrodes are connected through the gold wire, and then the silica gel mixed with the phosphor powder is placed on the upper point, and the white light is generated after being lit. .
There are three disadvantages to this product:
1. The gold wire is easily broken by the thermal expansion and contraction of the silica gel;
2. The shape of the silica gel affected by the gold line curvature affecting the mixed phosphor is difficult to control, resulting in uneven distribution of the phosphor;
3. The chip is grown on a sapphire substrate. The thickness of the chip is about 8 μm, and the thickness of the sapphire is about 150 μm. The heat of the chip is transmitted to the support through the sapphire. The path is long and the thermal resistance is large, and the heat dissipation performance is poor.
The appearance of flip chip can effectively solve the above problems. The package of flip chip is commonly called gold-free package. There is no gold wire to effectively solve the first and second problems. At the same time, the flip chip layer is directly bonded to the substrate, sapphire. It is no longer used as a heat conduction channel, but as a luminescent medium, it avoids the problem of long heat conduction path and poor heat dissipation performance.
The advent of flip-chips has made planar coating technology available for LED packaging. Flat coating technology is generally used for semiconductor component packaging processes. There is no report of planar coating technology for LED packaging processes.
In this paper, the flip-chip package on a flat-coated white ceramic substrate is studied, and the front and back light distributions of the three-dimensional illumination are studied. The planar coating process with uniform light color is improved, and the optimal preparation of the stereoluminescent phosphor coating technology is obtained. .
experiment
The flip-chip LED chip is fixed on the white ceramic substrate by a die bonder. The size of the ceramic plate is 5 mm×8 mm×0.64 mm, and the size of the chip is 14 mil×30 mil. The sample after the chip is fixed is shown in FIG. 1 , and the glue and The phosphor ratio was: 1.1:1.1:1.28:0.095, labeled as Sample 1, Sample 2, and Sample 3.
Sample 1 is a flat phosphor coated directly on the front side;
Sample 2 is first filled with silica gel to fill the inter-chip gap, dried and then coated on the front side with a glue plane of mixed phosphor;
Sample 3 was first coated with interstitial voids coated with silica gel mixed with diffusion powder, dried and then coated on the front side with a glue plane of mixed phosphor, as shown in FIG.
Test equipment: The light color test was carried out on the front and back sides of the standard machine (model 0.3m integrating sphere); the light distribution was tested and analyzed by a remote distributed photometer.
Figure 1: Uncoated phosphor white ceramic plate after solid crystal
Figure 2: Photographs of Sample 1, Sample 2 and Sample 3
Analysis and discussion
For the sample 1 and sample 2, the front and back sides of the sample 3 are tested by a standard machine. The test method is to illuminate the sample, and the front or back side is close to the small hole on the integrating sphere, and the front and back transient photoelectric parameters are tested respectively. The transient color temperature, luminous flux and chromaticity coordinates are shown in Table 1.
It can be seen from Table 1 that the color temperature of the front and back sides of sample 2 is basically the same, the back side luminous flux is 13% of the front side, and the total luminous flux is 166.3 lm (@110 mA); the luminous flux of sample 1 is the highest, but the color temperature difference between the front and back sides is the largest (682K). The reverse side flux is only about 10% of the front side; the color temperature of sample 3 is basically the same, but the luminous flux is the lowest (125 lm), and the back side luminous flux is only about 10% of the front side.
It can be found from Fig. 3 that only 8 points fall in the normal bin area of ​​the CIE diagram of 2670-2850K, and only one point (the reverse side of the sample 1) falls outside the bin, indicating that the color coordinates of the reverse side of the sample differ greatly from the front side, and The color coordinates of the front and back sides of Sample 2 and Sample 3 are basically the same, in line with international standards.
The bottom end of the light source is attached to the heat sink, and the driving current is 110 mA, and the light flux, color temperature, and chromaticity coordinates of the tester are illuminated for 30 minutes, as shown in Table 2.
It can be seen from Table 2 that the color temperature of the front and back of all samples increases, indicating that the thermal quenching effect of the phosphor is greater than that of the chip, and the temperature of the thermal radiation is greater than the temperature of the chip; the luminous flux is decreased by 8%. About 10%, due to the steady state, the substrate temperature is higher than the transient test temperature, so its luminous flux shows a decrease.
Figure 4: Front and back drop plots of steady-state test samples
Figure 4 shows the falling bin chart of the front and back sides in steady state. From the figure, it can be found that the falling point is more concentrated, but the falling point of the negative side of the sample 1 is still outside the bin, and the remaining falling points are in the normal range. It indicates that the front and back of the steady-state test sample still meet international standards.
The illuminating angle and intensity of the front and back of all samples were tested using a distributed photometer as shown in Figure 5.
Figure 5: Luminous angle and intensity of the C0-180 surface on the front and back of all samples @30mA
From Fig. 5, it can be found that in all the samples, the front side of the sample 1 is the strongest of all frontal illuminance, and the reverse side of the sample 2 is the strongest of all the reverse illuminants.
The illuminating intensity of the reverse side of Sample 1 and Sample 3 was basically the same; the illuminating angle and shape of all the samples were the same, indicating that the addition of silica gel or diffusion powder did not affect the illuminating angle.
From the numerical analysis of luminous intensity, the reverse side of the sample is about 10% of the frontal luminous intensity, the reverse side luminous intensity of the sample 2 is about 15% of the front side, and the reverse side luminous intensity of the sample 3 is about 9% of the front side.
The combination of the front and back strengths revealed that the overall luminescence intensity of the sample 1 was the largest, the overall luminescence intensity of the sample 2 was about 80% of the sample 1, and the overall luminescence intensity of the sample 3 was about 60% of the sample 1. The luminous flux ratio is substantially the same as the above-described integrating sphere test.
in conclusion
The three-dimensional LED lamp piece was prepared by three kinds of processes, and through the study of its luminous flux, color temperature, color coordinate and illuminating angle, it was found that:
The LED stereo light source (sample 1) prepared by directly coating the phosphor directly has the highest overall luminous flux, but the front reflective flux differs by nearly 10%, and the color temperature and color coordinate are greatly different, which is not suitable for actual production;
The product prepared by first coating the silica gel and then coating the phosphor powder has no high luminous flux, but the color temperature, color coordinate and light distribution of the front and back sides are small, which is suitable for preparing high-quality LED stereo light source;
The products prepared by first applying the doped diffusion powder silica gel and then coating the phosphor powder process have little difference in color temperature and color coordinates, but the overall luminous flux is as low as 60% of sample 1 and 75% of sample 2.
100M 8+2 port passive POE Switch for IP camera
STD-POE5203-10 supports data and power transmission through CAT.5 cables at the same time. And 8+2 port support fast connecting at 100/1000Mbps. It also supports long transmission distance at 250 meters both for power and data, therefore, it saves cost for the project that requiring long distance transmission through extender, fiber and coaxial cable etc. It reduces line losses effectively though 8-core cable supplying power same time. Max power for each port is 30W, which is for IP Camera and POE wirelessaccess point etc.
Features:
REVERSE POE TECHNOLOGY:8 Port 10/100 Reverse POE switch which has latest generation of fast Ethernet reverse POE switching technology. It contains 7*10/100 base T Reverse Poe ports (RPOE),1*10/100 Base date Uplink Port&12V DC out for Powering ONU.
Supports Auto-Negotiation: Each of the ports automatically detect whether connected network devices are running at 10Mbps or 100Mbps and half-duplex or full-duplex mode, and adjusts the speed and mode accordingly ensuring easy and hassle-free operation.
Supports Non-blocking Wire Speed: The switch forwards and receives traffic seamlessly with its Non-blocking wire- speed. Every port of the Switch supports speeds up to 200Mbps in full-duplex mode simultaneously, providing full wire speed to connected devices and allowing you to run a high speed network smoothly.
Cascading support: switches can be cascaded for more users per Building (Up to 1 Main+3 switches )
Port base Isolation u/Hardware VLAN: The feature of Port Isolation is implemented in this unit where in the Ethernet Date of the Uplink Port can be transferred to any of the Downlink ports but the individual Downlink ports cannot communicate with each other.
Over voltage Protection:
Over voltage Protection is provided on each date port to eliminate damage due to connection of higher voltage(Higher than 24V DC. Up to 80V DC). By mistake if user connect more than 24V POE injector then switch will goes on power off mode and will start working again once this high voltage source is removed.
Over current Protection: We have provided over current protection on each port to prevent damage to the switch in case of high current flowing due to any reason. This is provided using Resettable Fuse to facilitate easy maintenance and avoiding frequent change of blown fuse.
Product Application:
7*10/100 Base T Reverse POE Ports(RPOE) & 1*10/100 Base T Uplink Port & 12V DC Power out for Powering ONU
Product Images:
POE Switch,POE Switches Puzzle,POE Switches 4 Port,100M POE Switch
Guangdong Steady Technology Co.LTD , https://www.steadysmps.com